`timescale 1ns / 1ps

`include "CHECKER8bit.v"
`include "BINARYSEARCH8bit.v"
module MAIN ();

	reg clk;
	wire[7:0] result;
	wire is_activated;
	wire[1:0] cond;

	BINARYSEARCH8bit uut1 (
		.clk(clk),
		.cond(cond),
		.result(result),
		.is_activated(is_activated)
	);

	CHECKER8bit #(.param(8'd120)) uut2 (
		.num(result),
		.result(cond)
	);

	initial begin
		$monitor("time=%0t, result=%d, is_activated=%b", $time, result, is_activated);
		clk = 0;
		while (is_activated != 1'b1) begin
			#5 clk = ~clk;
		end
	end
endmodule